Organized by: Department of Electrical &Electronics Engineering
College Website: www.mcet.in/
CoreEL achieves this by providing state of the art products from XILINX, MENTOR GRAPHICS, MATLAB, VxWorks (WIND RIVER), ANSYS, Speedgoat (Rapid Controller Prototyping and Hardware-in-the-Loop simulation) and Analog Discovery Kits from Digilent to universities and provide application engineering support on these products. In addition CoreEL supports in providing Faculty and student training, industry specific inputs to update the curriculum and setting up Centres of Excellence in VLSI and Embedded Systems arena.
Resource Persons
Ms.Sadiya,
NationalManager,
Mr.G.Prakash,
Technical Support Specialist,
Mr.Senthil Murugan V,
Zonal Manager,
CoreEL Technologies, Bangalor
ELIGIBILITY
Faculties from AICTE approved Engineering Colleges
with relevant background, Candidates from industries,
R & D organizations and PG students in related
discipline are eligible.
PRE-REQUISITES
Digital logic and FPGA design experience
Basic experience with Verilog and VHDL
Basic understanding of C programming
COURSE HIGHLIGHTS
Architect an embedded system targeting the ARM, processor of Zynq Device using Vivado and IP Integrator
Extend the hardware system with Xilinx provided peripherals
Create a custom peripheral and add it to the system,Debug a design using Vivado hardware analyzer
Use Vivado HLS to generate an IP-XACT compliant
hardware accelerator.
COURSE CONTENT:
Day 1:
7-series FPGA Architecture Overview
Vivado Design Flow
Lab 1: Creating a HDL Design (VIVADO)
Lab 2: Xilinx Design Constraints
IP Integrator and Embedded System Design Flow
Lab 3: Create a Processor System using IP Integrator
Day 2:
Embedded System Design with Custom IP
System Debugging using Vivado Logic Analyzer and
SDK
Lab 4: Debugging using Vivado Logic Analyzer cores.
Profiling and Performance Improvement
Introduction to High-Level Synthesis with Vivado HLS, Improving Performance and Resource Utilization
Creating an Accelerator
Lab 5: Creating a Processor System using
Accelerator
Lab 6: Filter Design using Xilinx Vivado
SystemGenerator.
Registration Details:
Category Registration Fee
Faculty member/ Research Scholar Rs.750/=
UG/PG Scholar Rs.500/=
Registration is strictly limited to 30 participants.
Organizing Committee:
Convener
Dr.A.Senthilkumar
Prof. & Head/EEE
Co-ordinator:
Dr. K. N. Vijeyakumar
Associate Professor / EEE
Co- Coordinators:
Ms. K. Saranya, Ms. M. Sangeetha & Ms.R.Divya
Assistant Professors / EEE
How to Apply?
The applicant should send his/ her application in the specified format along with Demand Draft(DD) to reach us
on or before 23/01/2016. DD should be drawn in favour of “The Principal, Dr.MCET, Pollachi” payable at Pollachi.
The registration fee includes workshop kit, refreshment and lunch.
Email: vijey.tn@drmcet.ac.in
Mobile Number: 9942377050 / 9715397453
