HomeEventsWorkshopsInternational workshop Conducted by Centre for Development of Advanced Computing

International workshop Conducted by Centre for Development of Advanced Computing

Institution Name: Centre for Development of Advanced Computing

Event Type: Workshop

Event Name: International workshop on RISC-V for HPC (RISCV-HPC) at HiPC 2025

Event Start Date: 17-12-2025

Event End Date: 17-12-2025

Event Organizing Department: Department of Mining Engineering

About the Event :

RISC-V is an open, modular, and extensible Instruction Set Architecture (ISA) that is rapidly gaining global attention for its potential to foster innovation across computing domains. Its royalty-free nature and open governance model encourage collaboration among academia, industry, and research institutions. While RISC-V has already seen significant success in embedded systems, IoT devices, and edge computing, its possibilities for High-Performance Computing (HPC) are only starting to emerge.

HPC continues to drive breakthroughs in science, engineering, and data analytics by enabling complex simulations, large-scale computations, and machine learning workloads. The growing need for energy-efficient, customizable, and high-performance solutions makes RISC-V an attractive option. Recent developments such as the standardization of vector extensions, advancements in cache coherence mechanisms, and the evolution of high-speed interconnects have enhanced RISC-V’s readiness for demanding HPC applications. These innovations present new opportunities to design processors and systems that meet the diverse needs of supercomputing.

This workshop aims to provide a platform for researchers, hardware designers, system software developers, toolchain maintainers, application scientists, and integrators to exchange ideas on the role of RISC-V in HPC. The event will feature discussions on experiences from early deployments, performance evaluations, architectural innovations, and software ecosystem enhancements. We particularly welcome participation from academic institutions, industry experts, government research labs, and non-profits across India, Asia, and the global HPC community.

By focusing on both the challenges and the potential of RISC-V for HPC, this workshop seeks to build connections among stakeholders and promote open hardware in supercomputing. Our goal is to inspire future architectures and solutions that are open, flexible, and driven by community collaboration, complementing HiPC’s mission to advance state-of-the-art HPC research.

Registration Fee:
Category Indian National (INR) Foreign National (USD) Offline Foreign National (USD) Online
Student Delegate 10000 125 75
Professional Delegate from Academia and Industry 18000 225 125

Submission link : https://easychair.org/conferences?conf=riscvhpc2025

Important Dates:

For all queries, please contact: riscvhpc2025[at]cdac[dot]in

Event Website: Click here

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